Unlike the Master-Slave design, which needs a complete pulse, you can also build an edge-triggered design that triggers from a rising edge ↑ or a falling edge ↓. That’s why this configuration is called pulse-triggered JK Flip-Flop. 4 bit counter (IC-7476 is being used for this purpose as T-flip flop) 2. So this circuit requires a complete pulse (0→1 →0) in order to change the output. Once the clock signal produces a falling edge ↓, a change from 1 to 0 (1→0), it triggers the slave section, causing the Q output to reflect the master’s output value. These signals are connected to the slave section, but this doesn’t trigger on the rising edge because the clock has been inverted. As a result, the value of the outputs in this section changes. As soon as the clock makes a rising edge ↑, which is a change from 0 to 1 (0→1), it triggers the master section.
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